Many elements of a chip (or integrated circuit) require a periodic signal such as a clock signal to ensure proper operation and timing of the elements of the chip. The clock signal can be a periodic signal having a duty cycle such as a 50% duty cycle (i.e., the signal is in a logical 1 state for the same amount of time that it is in the logical 0 state). In some instances, a clock signal may experience unexpected glitches during transitions from high to low or from low to high (i.e., transitions between a logical 1 and a logical 0 that are not intended as part of the period or duty cycle of the clock signal). These glitches may be of a short duration at the rising and falling edges of the clock signal. In some cases, unexpected glitches may disrupt the operation of the elements of the chip and can result in timing issues that can lead to further disruptions in the operation of the elements of the chip.
A payment terminal can include one or more chips with components requiring clock signals that are used to process payment transactions and interact with payment devices such as a payment card having a magnetic strip that is swiped in a magnetic reader of the payment terminal, a payment device having a Europay/Mastercard/Visa (EMV) chip that is inserted into a corresponding EMV slot of the payment terminal, and near field communication (NFC) enabled devices such as a smartphone or EMV card that is tapped at the payment terminal and transmits payment information over a secure wireless connection. In order to ensure accurate processing of payment transactions, stable operation of the chips in the payment terminal is required. Merchants and consumers attempting to complete a payment transaction may become frustrated if errors occur during payment transactions or the payment transactions are not otherwise processed accurately due to unstable operation of the chips in the payment terminal.